1. Field of the Invention
The present invention is related to a solid-state imaging apparatus.
2. Description of the Related Art
Conventionally, amplification type solid-state imaging apparatuses are known in technical fields, in which photoelectric conversion elements and amplifying units are included in pixels, while the amplifying units amplify signals produced based upon electric charges of the photoelectric conversion elements. Among the above-mentioned amplification type solid-state imaging apparatuses, general structures thereof are constructed by providing transfer switches and reset switches in input portions of the amplifying units, while the transfer switches transfer electric charges of the photoelectric conversion elements, and the reset switches reset the input portions of the amplifying units.
As a solid-state imaging apparatus having an electronic shutter function, Japanese Patent Application Laid-Open No. H08-336076 has disclosed such a structure which includes a vertical scanning circuit for controlling transfer switches, and another vertical scanning circuit for controlling reset switches. In the above-mentioned solid-state imaging apparatus having the electronic shutter function of Japanese Patent Application Laid-Open No. H08-336076, the scanning operation of the reset scanning-type vertical scanning circuit is performed at a certain time, whereby the respective pixels are reset. Thereafter, since the scanning operation of the transfer scanning type vertical scanning circuit is performed at another time, an accumulation time period, namely, a shutter time period can be determined (namely, electronic shutter).
Also, Japanese Patent Application Laid-Open No. 2005-094142 has disclosed an arrangement in which reset scanning circuits capable of performing resetting operations two times within 1 frame have been arranged in a dual system in order to solve such a problem that when a scaling factor is switched during electronic zooming in a structure for performing an electronic shutter, exposure time periods are different from each other every row.
However, in the dual system arrangement of Japanese Patent Application Laid-Open No. 2005-094142, there is such a problem that the circuit scale of the reset vertical scanning circuit is increased. The reset scanning circuits arranged in the dual system are alternately operated every time a timing signal is output from a timing control unit. As a consequence, it is required to construct that both the reset scanning circuits arranged in the dual system can access with respect to all rows of pixel regions. Both the reset scanning circuits capable of accessing all of those rows are arranged, and hence the circuit scale is increased, and the chip area is increased. Otherwise, a degree of freedom as to an element layout is decreased. In some cases, the above-mentioned accessible arrangement of the reset scanning circuit may conduct that an area of pixel regions is decreased.
The present invention has been made to solve the above-mentioned problems, and has an object to provide such a solid-state imaging apparatus capable of performing reset scanning a plurality of times within 1 frame without increasing a circuit scale of the solid-state imaging apparatus.